Quantum Bayesian Networks

May 7, 2011

Intel Waffles

Filed under: Uncategorized — rrtucci @ 5:29 am

The word “waffle” used as a verb means to waver, vacillate, avoid commitment, sit on the fence. Example:

Intel waffles about quantum computers.

Used as a noun, waffle means the tasty latticework breakfast molded with a waffle iron (alas, not so common in American households anymore). Example:

Intel is now producing transistors shaped like waffles.

This blog post is about the second usage. (The first usage was discussed in a previous blog post.)

Recently, the news media has been abuzz with news about Intel’s new 3D Trigate transistors. Check out, for example,

The YouTube video has some nice visuals. I highly recommend it. The AnandTech article is excellent too, and a little bit more technical.

Each transistor in a computer is analogous to a tiny valve that can shut ON or OFF the flow of water (= flow of electrons = current) in a pipe (=wire). Such a valve (=gate=barrier) can be switched ON and OFF at a certain switching rate. The faster the switching rate, the higher the power dissipation.

Until now, Intel and everyone else have been making pipes whose cross section looked like a dash; that is, like a skinny rectangle with one dimension much larger than the other. Starting with its 22nm node-length microprocessors due out before the end of this year, and thereafter, Intel will be making transistors in which the cross-section of the pipe looks like the letter U instead of a dash.

Even though a U and a dash are topologically the same, the U-cross-section pipe is preferable because it can carry more current. If the length of the dash is the same as the horizontal, bottom side of the U, then the U can carry current along 3 sides instead of just 1. Not only is a U-cross-section pipe more efficient at carrying current, but the valve to block the pipe is more efficient too, because it pinches the flow on 3 sides instead of 1. This is the reason why Intel calls it a 3D Trigate, because the gate has 3 sides, the 3 sides of the U. Other people call such transistors fin gates or FinFETs, because the U resembles a fin (a FET is a type of transistor). I like to refer to the older, non-fin gates as “flat gates”.

For any transistor, the faster the switching rate F, the higher the power dissipation P. For a fixed P, the fin gate allows higher F than the flat gate at fixed node-length. And for a fixed F, it allows a lower P. This is all explained more nicely and more quantitatively in the AnandTech article.

When the valve is shut OFF, an electron that leaks across the barrier has to tunnel across a barrier of a certain thickness and energy-height. The thickness of the barrier is a fraction (something like 1/2) of the node-length figure. For example, once Intel gets to 11nm node-length, which they plan to do by 2015, the barrier thickness will be about 5nm, which is about 10 Silicon atoms thick.

Moore’s Law
Moore’s Law says that the transistor density of widely available chips doubles every two years. Thus, Moore’s Law describes how the transistor density (which is proportional to the inverse of the squared node-length) varies with time. Intel plans to use fin gate transistors on all chips with node-lengths smaller or equal to 22nm. The fin gates are more efficient than the flat gates at a fixed node-length, but this is not expected to change the plans for how node-length will decrease with time. Therefore, this new type of gate will not affect much the inexorable progress of Moore’s Law. Intel and the rest of the microprocessor industry are still planning to reach 11nm node-lengths by 2015. The only difference is that this node-length will now be reached with fin gates instead of flat gates.

Of course, it might be possible to stack layers of these waffles on top of each other, but that approach is fraught with its own perils. Such stacks will store a lot of heat between the layers, and it might be very difficult to remove that heat quickly enough so as not to markedly degrade the performance of the chip or even melt it.

So, what does this all have to do with quantum computers?
Note that both a fin gate and a flat gate have the same barrier thickness (and the same(?) barrier energy-height) at a fixed node-length. That barrier thickness will be about 5nm for the 11nm node-length. Since quantum tunneling only depends on the barrier thickness and barrier energy-height, I think we can expect about the same amount of quantum tunneling with both fin and flat gates at 11nm node-length. So reaching node-lengths below 11nm will still require a paradigm shift other than fin gates (perhaps quantum computing?). To paraphrase the movie King Kong: Twasn’t the planes (geometry) that got him, boys, twas the beauty (of quantum tunneling and quantum mechanics) that killed the beast (of Moore’s Law).


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